1. Technical Field
Embodiments of the invention generally relate to the field of integrated circuits and more particularly, but not exclusively, to communication of error detection information with a memory device.
2. Background Art
Memory devices are susceptible to errors such as transient (or soft) errors. If these errors are not handled properly, they can cause a computing system to malfunction. Redundant information in the form of error correcting codes (ECCs) can be used to improve overall system reliability. Typically, a memory controller performs error correction coding operations to generate and/or evaluate such redundant information for a plurality of data bits.
The redundant information is often stored in the memory with the corresponding plurality of data bits to allow the memory controller to recover the plurality of data bits if errors are introduced in one or more of the plurality of data bits during transmission to/from the memory or while being stored in the memory. The redundant information, however, increases the storage requirement of the memory system and, thereby, increases the cost of the memory system. Thus, ECC is typically used for comparatively high-end or mission critical applications.
Recently, error detection logic has been incorporated on-die with integrated memory circuit devices. On-die ECC can correct single bit errors before a controller or other external agent reads the data. Increasing occurrences in data errors are associated with failure, or expected future failure, of a memory device. On-die errors are likely to have an increasing impact on memory performance as the fabrication processes such as those for dynamic random access memory (DRAM) circuitry continues to scale to smaller geometries. Therefore, access to data error information from such memory devices is useful for platforms to anticipate possible memory failure.